1. Field of the Invention
The present invention relates to an apparatus for transmitting digital data which includes information data and synchronous data, and more particularly to an apparatus adapted for detecting a sync code in reproduced information data based on, for example, an ID-1 format.
2. Description of the Prior Art
A known apparatus designed to perform a high-density recording of information data is based on an ANSI ID-1 format (Third Draft, PROPOSED AMERICAN NATIONAL STANDARD 19 mm TYPE ID-1 INSTRUMENTATION DIGITAL CASSETTE FORMAT X3B6/88-12 Project 592-D 1988-03-22).
In such a data recorder, error correction of the information data is effected by employing a product encoding notation with a Reed-Solomon code and then recording it on a magnetic tape, so that, in a playback mode, any transmission error may be thereby detected and corrected.
The ANSI ID-1 format used in the known data recorder will now be further described below:
FIG. 1 diagrammatically illustrates an example of a recording pattern formed on a magnetic tape by the data recorder based on the ID-1 format. In this diagram, ANN indicates an annotation track for recording notes thereon, and data tracks TR1, TR2, TR3, . . . are for recording information data, with one sector being formed for each data track. The data tracks are recorded with alternately different azimuth angles. Further shown are a control track CTL for recording a control signal, and a time code track TC for recording a time code.
The content of each of the data tracks TR1, TR2, TR3, . . . is prescribed as illustrated in FIG. 2. Specifically, each data track TR corresponds to one sector SEC and is constituted by a preamble PR, a data recording portion DT and a postamble PS. The preamble PR is recorded in the top portion of the respective data track formed obliquely across the tape.
Each preamble PR is composed of a 20-byte ascending sequence RUS, a 4-byte sync code SYNC.sub.PR, 4-byte sector identification data ID.sub.SEC1, and 6-byte auxiliary data DT.sub.AUX.
Each data recording portion DT is composed of 256 sync blocks BLK (BLK.sub.0, BLK.sub.1, BLK.sub.2, . . . BLK.sub.255), and the input information data is recorded in this portion DT. Each sync block BLK consists of a 4-byte block sync code SYNC.sub.BLK, a 1-byte block identification ID.sub.BLK, 153-byte inner data DI (inner-coded input information data) and an 8-byte parity code RI based on Reed-Solomon code notation.
Each postamble PS is composed of 4-byte sync code SYNC.sub.PS and 4-byte sector identification data ID.sub.SEC2.
FIG. 3 shows a recording system 1 of the ID-1 format data recorder. In this recording system 1, the input information data is recorded after being encoded for error correction by a product code notation.
More particularly, 8-bit (1-byte) input information data DT.sub.USE is supplied to an outer encoder 2. By the use of a predetermined generating polynomial with regard to the data blocks each composed of 118 bytes of the input information data DT.sub.USE, the outer encoder 2 generates outer codes which are parity codes RO.sub.0 -RO.sub.305 each composed of 10-byte Reed-Solomon code. As shown schematically on FIG. 4, such outer code is added to the end of each data block, which is thereafter outputted as an outer data block DO.
The outer data block DO is fed through a first multiplexer 3 to a memory unit 4. As shown in FIG. 5, the memory unit 4 consists of memories MEM1 and MEM2 each having each capacity of 154 bytes in a row and 128 bytes in each column. In this example, 153 outer data block DO.sub.0 -DO.sub.152 inputted sequentially are stored in the memory MEM1, while next 153 outer data blocks DO.sub.153 -DO.sub.305 inputted sequentially in succession after the outer data blocks DO.sub.0 -DO.sub.152 are stored in the memory MEM2 in such a manner that one outer data block is written in each column. The information data of one outer data block is composed of 118 bytes and, since 153 blocks of the information data are written in each of the memories MEM1 and MEM2, it follows that a total of 118.times.153.times.2 bytes (=36,108 bytes) of the information data are written in the memory unit 4.
The data writing direction in each column of the memories MEM1 and MEM2 is indicated by an arrow ARW1 in FIG. 5, and the lower 10 bytes in each column of the memories MEM1 and MEM2 correspond to the outer error code OR.
Data block identification data ID.sub.B generated by an identification data generator 5 for identifying the individual rows in the memories MEM1 and MEM2 are also supplied through the multiplexer 3 to the memory unit 4. Even components ID.sub.BE of such data block identification data ID.sub.B are written in the memory MEM1 while odd components ID.sub.BD thereof are written in the memory MEM2 column by column in the direction ARW1.
The data thus written in the memories MEM1 and MEM2 are read out therefrom in the direction ARW2 (FIG. 5) in such a manner that the data of each row is processed as one block. The data reading operation for individual rows is performed alternately, with respect to the memories MEM1 and MEM2, in the order conforming to the data block identification data ID.sub.B (00, 01, 02, 03, . . . ). The data read out from the memories MEM1 and MEM2 are inputted to an inner encoder 6 (FIG. 3).
Through the use of a predetermined generating polynomial with respect to each of the input data blocks, the inner encoder 6 generates inner or parity codes generating polynomial with regard to each of the input data blocks, inner codes which are parity codes RI.sub.0 -RI.sub.255 which each contain an 8-byte Reed-Solomon code. As shown in FIG. 6, such inner codes R1 are added to the ends of the respective data blocks to form inner data blocks DI.sub.0 -DI.sub.255, which are then outputted to a second multiplexer 7.
The second multiplexer 7 selectively outputs the preamble data PR and the postamble data PS formed by a preamble/postamble generator 8 and also the inner data blocks DI.sub.0 -DI.sub.255 outputted from the inner encoder 6. Such data are outputted in the order of the preamble data PR, the inner data blocks DI.sub.0 -DI.sub.255 and the postamble data PS. The output of the second multiplexer 7 is fed to a data randomizer 9.
In the data randomizer 9, the data are randomized through the application of an exclusive OR with regard to every byte of the input data and predetermined data. The data thus randomized is inputted to an 8-9 modulator 10.
In this modulator 10, the data are converted from an 8-bit combination to a 9-bit combination for the purpose of achieving a DC-free state by the removal of the DC component from the signal waveform to be recorded on the magnetic tape. Such conversion is performed in the following manner. For each of 256 values of the input data in which each byte is composed of 8 bits, two kinds of 9-bit data are predetermined on the basis of the ID-1 format. Such two kinds of 9-bit data have codeword digital sums (CDS) which are different from each other in polarity. The 8-9 modulator 10 monitors the digital sum variation (DSV) of the 9-bit data outputted in accordance with the input data and selects either of the two kinds of 9-bit data having different CDS values, in such a way as to reduce the DSV value to zero. Thus, the 8-bit input data are converted into DC-free 9-bit data. The 8-9 modulator 10 also includes a circuit for converting the input data of NRZL (non-return to zero level) form into that of NRZI (non-return to zero inverse) form. The 9-bit output data of the 8-9 modulator 10 in NRZL form are inputted to a third multiplexer 11.
In the third multiplexer 11, a sync code SYNC.sub.B of a fixed 4-byte length obtained from a sync code generator 12 (FIG. 3) is added to each of the inner data blocks DI.sub.0 -DI.sub.255 for forming sync blocks BLK.sub.0 -BLK.sub.255. The pattern of such sync code SYNC.sub.B is determined on the basis of the ID-1 format, and the pattern to be recorded on the magnetic tape is so prescribed as to conform with such code pattern.
The data obtained in the above processes is shown in the form of maps MAP1 and MAP2 in FIG. 7. The output of the third multiplexer 11 has a data array obtained by scanning such maps MAP1 and MAP2 in the horizontal direction. The output of the third multiplexer 11 is fed to a parallel-to-serial converter 13 (FIG. 3).
In the parallel-to-serial converter 13, the input bit-parallel data of preamble PR, sync blocks BLK.sub.0 -BLK.sub.255 and postamble PS (FIG. 2) are converted into bit-serial data S.sub.REC. Such serial data S.sub.REC is amplified by a record amplifier 14 and then is supplied as a record signal to a magnetic head 16 which scans the magnetic tape 15 in a helical scanning mode, whereby record tracks TR ( . . . , TR1, TR2, TR3, TR4, . . . ) are obliquely formed on the magnetic tape 15 as illustrated in FIG. 1.
In this manner, the recording system 1 in the data recorder is adapted to add an error correction code, which is based on the Reed-Solomon product code notation, to the desired information data DT.sub.USE to be recorded.
The information data DT.sub.USE thus recorded on the magnetic tape 15 by the recording system 1 of the data recorder is reproduced by a reproducing system 20 of the data recorder shown in FIG. 8.
The signal processing operation in the reproducing system 20 is exactly inverse to the operation performed in the recording system 1.
In the reproducing system 20 of the data recorder, the record tracks TR ( . . . , TR1, TR2, TR3, TR4, . . . ) on the magnetic tape 15 are reproduced by the magnetic head 16 to become a playback signal S.sub.PB, which is then inputted to a playback amplifier 21.
The playback amplifier 21 comprises an equalizer and a binary encoder, wherein playback digital data DT.sub.PB is obtained by encoding the input playback signal S.sub.PB in a binary notation and then is outputted to a serial-to-parallel converter 22. In this converter 22, the serial playback digital data DT.sub.PB is converted into 9-bit parallel data DT.sub.PR.
In a sync code detector 23, the 4-byte sync code SYNC.sub.B is detected from a stream of the parallel data DT.sub.PR, and the sync block is identified in accordance with the detected sync code. The sync code detector 23 includes a circuit for converting the NRZI-form parallel data DT.sub.PR into NRZL-form data.
The output of the sync code detector 23 is fed to a 9-8 demodulator 24, where the data processed by 8-to-9 bit conversion to be rendered DC-free in the recording system is demodulated to provide 8-bit data again. The demodulator 24 may be composed of a ROM (read-only memory) which converts the 9-bit data to 8-bit data by a table retrieval process.
The 8-bit data thus obtained are derandomized in a derandomizer 25 through a process which is the inverse of the randomization executed in the recording system. Such derandomization is achieved by calculating an exclusive OR of the predetermined data used for the randomization and the input data fed to the derandomizer 25.
An inner code error detector/corrector 26 performs error detection and correction by using the 8-byte inner code RI.sub.0 -RI.sub.255 added respectively to the inner data blocks DI.sub.0 -DI.sub.255 of the identified sync blocks.
The inner data blocks DI.sub.0 -DI.sub.255 subjected to such inner code error correction are written in a memory unit 28, which is structurally the same as the aforementioned memory unit 4 (FIG. 5) of the recording system. Such writing in the memory unit 28 is controlled on the basis of the 1-byte block identification data ID.sub.B added to each block detected by an identification data detector 27, in such a manner that one data block is written in one row. The data writing order is the same as the order of reading out the data from the memory unit 4 in the recording system, and the data blocks are written in the memories MEM1 and MEM2 row by row alternately in conformity with the block identification data. The data thus written in the memories MEM1 and MEM2 of the memory unit 28 are read out therefrom in the direction of columns in the same order as the data writing order in the memory unit 4 of the recording system, and consequently the 128-byte outer data blocks DO.sub.0 -DO.sub.306 are recovered.
In an outer code error detector/corrector 29, error detection and correction are performed, with regard to the outer data blocks DO.sub.0 -DO.sub.306 outputted from the memory unit 28, by using the 10-byte outer code RO.sub.0 -RO.sub.306 added to the respective data blocks.
Thus, the information data DT.sub.USE recorded on the magnetic tape 15 is reproduced in the manner described above.
In the reproducing system 20 of the data recorder constituted as described above, the playback digital data DT.sub.PB inputted in the form of serial data are first converted into parallel data DT.sub.PR by the serial-to-parallel converter 22 and then are supplied to the 9-8 demodulator 24.
In the serial-to-parallel converter 22, various sync codes SYNC inserted at the interval of every predetermined byte length of the playback digital data DT.sub.PB are detected, and serial-to-parallel conversion is executed.
More specifically, as shown in FIG. 9, in a reproducing circuit 30, the playback digital data DT.sub.PB in serial form are inputted to both a serial-to-parallel converter 31 and a sync detector 32. In the sync detector 32, the timing of the sync code SYNC included in the playback digital data DT.sub.PB is detected, and the sync detection signal S.sub.SYNC obtained as a result of such detection is fed to a sync interpolator 33.
The sync interpolator 33 includes a flywheel counter and, in case the sync code SYNC fails to be detected due to some error, the sync detection signal S.sub.SYNC is interpolated in the time series mode, and simultaneously any false sync detection signal ES.sub.SYNC generated at an improper timing due to some error is masked.
The proper sync detection signal S.sub.SYNC thus interpolated is inputted to the serial-to-parallel converter 31, where the playback digital data DT.sub.PB in serial form is converted to parallel data DT.sub.PB9 while being divided into for example, groups of 9 bits at the timing of the proper sync detection signal S.sub.SYNC. Subsequently, the parallel data DT.sub.PB9 thus obtained is demodulated to parallel data DT.sub.PB8, of which each byte is composed of 8 bits, by the 8-9 demodulator 34, and then is written in a memory 35 having a memory matrix such as has been previously described in connection with FIG. 5.
In the circuit 30, the sync detection signal S.sub.SYNC is fed to the serial-to-parallel converter 31 while being fed also to a block counter 36 consisting of row counters and column counters, thereby controlling the write addresses ADR.sub.WR of the parallel data DT.sub.PB8 with regard to the memory 35.
It is generally customary that the sync code SYNC processed in the circuit 30 is composed of 1 or 2 bytes, and therefore the probability of failure in detecting the sync code SYNC due to some error is relatively low, whereas the probability of generation of a false sync detection signal ES.sub.SYNC at an improper timing is relatively high.
However, in the magnetic data recorder employing the ID-1 format, each of the sync, codes SYNC including the sync code SYNC.sub.PR of the preamble PR, the sync code SYNC.sub.BLK of the 256 sync blocks BLK in the data recording portion DT, and the sync code SYNC.sub.PS of the postamble PS, is determined to be 36 bits constituting 4 bytes composed respectively of 9-bit data.
Therefore, in the case of employing the ID-1 format, the probability of generation of a false sync detection signal ES.sub.SYNC is extremely low, whereas the probability of failure in detecting the sync code SYNC due to some error is high. The foregoing results from the fact that, as mentioned above, the sync code SYNC has a length of 36 bits.
In practice, if the initial sync code SYNC (i.e., the sync code SYNC.sub.PR of the preamble PR) of one sector SEC corresponding to one track fails to be properly detected, it is impossible to detect the block sync codes SYNC.sub.BLK of succeeding several blocks, so that thereby cause an error results.
In such case, although the inner data DI itself in the sync block BLK is normal, due to the decision signifying the existence of an error in the block sync code SYNC.sub.BLK, the inner data DI also is considered to be erroneous.